Design of hierarchical testable digital architecture

This paper presents a way of designing a hierarchical architecture used for testing using IEEE Standard 1149.1. The architecture is testable from the uppermost board level to the lowermost macro level. The architecture also incorporates a built-in self-test (BIST) capability at the macro level. Boundary San Standard is used at the board level to improve the controllability and observability of primary inputs and outputs of the integrated circuits. At the integrated circuit level the BIST is implemented. An integration of the boundary scan and the BIST is attempted, to give an architecture which is testable at different levels of hierarchy