Title :
Modified Gray And Counter Sequences For Memory Test Address Generation
Author :
Yarmolik, S.V. ; Yarmolik, V.N.
Author_Institution :
Belarusian State Univ. Of Informatics & Radioel.
Abstract :
The goal of this paper is to propose the new techniques for memory test address generation for pattern sensitive faults detection. It has been shown that the previous results based on the multiple runs memory testing are very efficient only for the first iterations. To achieve the high fault coverage the different types of modification have to be used. Two kind of memory address transformation have been proposed, analysed and experimentally validated
Keywords :
circuit testing; fault diagnosis; system-on-chip; counter sequences; high fault coverage; memory address transformation; memory test address generation; modified gray sequences; multiple runs memory testing; pattern sensitive faults detection; Built-in self-test; Circuit faults; Circuit testing; Counting circuits; Fault detection; Informatics; Manufacturing; Random access memory; Read-write memory; Test pattern generators;
Conference_Titel :
Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference
Conference_Location :
Gdynia
Print_ISBN :
83-922632-2-7
DOI :
10.1109/MIXDES.2006.1706645
