DocumentCode :
2639687
Title :
[Front cover]
fYear :
2007
fDate :
16-20 April 2007
Abstract :
The following topics are dealt with: integrated circuit design; integrated circuit testing; design automation; design for testability for SoCs; performance modelling and synthesis of analogue/mixed-signal circuits; system level mapping and simulation; IP designs for media processing; microprocessors in era of terascale integration; statistical/nonlinear analysis and verification for analogue circuits; nano-technologies for reconfigurable computing; LDPC codecs for communication standards; NoCs testing; automatic synthesis of computation intensive application specific circuits; automotive applications; test generation for diagnosis, scan testing and advanced memory fault models; process aware low power circuit design; hardware implementation of MPSoCs and NoCs architectures; ubiquitous communication and computation; industrial system designs in aerospace, avionics and automotive; mixed-signal and RF test; power management; embedded processors design; nano and FIFO; system level validation; model-based design for embedded systems; resource optimisation for best effort and quality of service; designs in avionics, military and space; timing analysis; middleware; secure systems; reliable microarchitectures; formal verification; interconnect extraction and synthesis; placement and floorplanning; crypto blocks and security; variation tolerant mixed signal test; SAT techniques for verification; compiler techniques for customisable architectures; interconnect optimization and metastability; physical and device simulation; wireless communication and networking system implementation; soft error evaluation; memory and instruction-set customization for real-time systems; order reduction and variation-aware interconnect modelling; system reliability; statistical timing and worst-delay corner analysis
Keywords :
analogue integrated circuits; automotive electronics; avionics; electronic design automation; embedded systems; formal verification; high level synthesis; integrated circuit design; integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; low-power electronics; microprocessor chips; mixed analogue-digital integrated circuits; nanoelectronics; network-on-chip; reconfigurable architectures; system-on-chip; FIFO; IP designs; LDPC codecs; MPSoC architectures; NoC testing; RF test; SAT techniques; SoC; advanced memory fault models; aerospace; analogue circuits; automotive applications; avionics; compiler techniques; computation intensive application specific circuits; crypto blocks; customisable architectures; design automation; device simulation; embedded processors design; floorplanning; formal verification; instruction-set customization; integrated circuit design; integrated circuit testing; interconnect extraction; interconnect optimization; metastability; microprocessors; middleware; mixed-signal circuits; model-based design; nano-technologies; placement; power management; process aware low power circuit design; quality of service; real-time systems; reconfigurable computing; reliable microarchitectures; scan testing; secure systems; soft error evaluation; statistical timing; statistical/nonlinear analysis; system level mapping; system level validation; system reliability; system-on-chip; terascale integration; test generation; timing analysis; variation tolerant mixed signal test; variation-aware interconnect modelling; wireless communication; worst-delay corner analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Conference_Location :
Nice
Print_ISBN :
978-3-9810801-2-4
Type :
conf
DOI :
10.1109/DATE.2007.364545
Filename :
4211750
Link To Document :
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