High speed small-area digital filter design using constrained quantization

It is widely known that constant coefficient multiplications can be efficiently realized using only shift and add operations. In addition, substantial gains in circuit area can be achieved by sharing the hardware units that are common among the filter coefficients. In this paper, a constrained quantization algorithm is proposed to increase the number of shared terms. By examples, it is shown that the use of the proposed quantization scheme can result in reduction in the number of binary adders up to 30%. In addition, it is shown that the critical path of an IIR filter can be reduced by constraining pole locations. The Remez exchange algorithm is used to compensate for the error introduced by pole location constraints. Thus, high performance IIR filter implementation can be achieved without any hardware overhead (with only slight degradation in frequency spectrum characteristics).