Design Of Decimation Filter For Multibit Sigmadelta Modulator With Two-step Quantization

Author

Kuncheva, A.S. ; Fujcik, L. ; Mougel, T. ; Donchev, B. ; Hristov, M.

Author_Institution

Sofia Tech. Univ.

fYear

2006

fDate

22-24 June 2006

Firstpage

646

Lastpage

649

Abstract

This paper describes steps involved in a VHDL design of digital decimation filter for multibit sigma-delta (SigmaDelta) modulator. Parameters of decimation filter are derived from the specification of the multibit SigmaDelta modulator with two-step quantization architecture. Using Matlab tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The design is programmed and tested on a Xilinx FPGA -Spartan 3 XC3S200-5FT256

Keywords

FIR filters; comb filters; field programmable gate arrays; hardware description languages; quantisation (signal); sigma-delta modulation; A/D conversion; Matlab tool; Spartan 3 XC3S200-5FT256; VHDL design; Xilinx FPGA; digital FIR/CIC filters; digital decimation filter; sigma-delta modulator; two-step quantization; Delta-sigma modulation; Digital filters; Digital modulation; Field programmable gate arrays; Finite impulse response filter; Frequency; Hardware; Quantization; Sampling methods; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference

Conference_Location

Gdynia

Print_ISBN

83-922632-2-7

Type

conf

DOI

10.1109/MIXDES.2006.1706663

Filename

1706663