Functional Level Implementation Of Evolvable Hardware Using Genetic Algorithms

Filtering data in real time requires dedicated hardware to meet demanding time requirements. One important feature of signal processing is coping with noise. To be able to achieve the required output signal for a wide range of input signals and noise, it is desirable to be able to adjust both the filter characteristics and the type of filter. In this way the resulting filter is said to be an adaptive filter. We propose an on-chip solution for evolving an adaptive digital filter using an on-chip evolvable hardware method. This project is about implementing evolvable hardware using genetic algorithms. It gives a formal introduction to evolvable hardware, which is a new hardware paradigm in which hardware is built on reconfigurable devices such as PLDs and FPGAs whose architectures can be reconfigured by using evolutionary computation techniques such as genetic algorithms, to adapt to the new environment