FPGA-based decoupled double synchronous reference frame PLL for active power filters

Decoupled double synchronous reference frame Phase-locked loop (DDSRF-PLL) is able to detect the phase angle of positive sequence when the three-phase voltages are unbalanced and distorted. In this paper, it is applied to the compensation current detection algorithm of shunt active power filter (SAPF) to replace a conventional PLL. Simulation results indicate that the compensation performance could be improved under voltage unbalance and distortion. Besides, DDSRF-PLL implemented on one field-programmable gate array (FPGA) chip is proposed. When compared with widely used digital signal processors (DSPs) in power control, FPGA the proposed structure has the advantages of parallel processing and rich user-defined I/O ports so that it exhibits processing efficiency and flexibility in application.