DocumentCode
2640091
Title
Implementation Of Bayesian Network In FPGA Circuit
Author
Kulesza, Z. ; Tylman, W.
Author_Institution
Tech. Univ. of Lodz
fYear
2006
fDate
22-24 June 2006
Firstpage
711
Lastpage
715
Abstract
The paper presents a novel approach to the implementation of Bayesian network - an implementation in an FPGA circuit. The opportunities and problems connected with the parallel-processing approach of the FPGA circuit are discussed. Modifications of the computation algorithm that are needed due to limited computational capabilities are described. Details of the construction of the main computational blocks are also depicted
Keywords
belief networks; field programmable gate arrays; logic circuits; parallel processing; Bayesian network; FPGA circuit; computational blocks; parallel-processing; probabilistic networks; Artificial intelligence; Bayesian methods; Circuits; Computer languages; Computer networks; Field programmable gate arrays; Hardware; Intelligent networks; Microcontrollers; Microprocessors;
fLanguage
English
Publisher
ieee
Conference_Titel
Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference
Conference_Location
Gdynia
Print_ISBN
83-922632-2-7
Type
conf
DOI
10.1109/MIXDES.2006.1706677
Filename
1706677
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