DocumentCode
2640198
Title
An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated Building Block Topology Selection
Author
Eeckelaert, Tom ; Schoofs, Raf ; Gielen, Georges ; Steyaert, Michiel ; Sansen, Willy
Author_Institution
Dept. of Electr. Eng., ESAT-MICAS, Leuven
fYear
2007
fDate
16-20 April 2007
Firstpage
1
Lastpage
6
Abstract
A hierarchical synthesis methodology for analog and mixed-signal systems is presented that fully in a novel way integrates topology selection at all levels. A hierarchical system optimizer takes multiple topologies for all the building blocks at each hierarchical abstraction level, and generates optimal topology combinations using multi-objective evolutionary optimization techniques. With the presented methodology, system-level performance trade-offs can be generated where each design point contains valuable information on how the systems performances are influenced by different combinations of lower-level building block topologies. The generated system designs can contain all kinds of topology combinations as long as critical inter-block constraints are met. Different topologies can be assigned to building blocks with the same functional behavior, leading to more optimal hybrid designs than typically obtained in manual designs. In the experimental results, three different integrator topologies are used to generate an optimal system-level exploration trade-off for a complex high-speed DeltaSigma A/D modulator
Keywords
delta-sigma modulation; evolutionary computation; mixed analogue-digital integrated circuits; modulators; building block topology selection; complex high-speed DeltaSigma A/D modulator; hierarchical synthesis; hierarchical system optimizer; integrator topology; mixed-signal systems; multiobjective evolutionary optimization; optimal topology combinations; Circuit synthesis; Circuit topology; Constraint optimization; Design optimization; Hardware design languages; Hierarchical systems; Hybrid power systems; Optimization methods; Stress; System performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Conference_Location
Nice
Print_ISBN
978-3-9810801-2-4
Type
conf
DOI
10.1109/DATE.2007.364571
Filename
4211776
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