Design of folded CCDs for ultra high speed imaging

The simplest idea to design an in-situ memory CCD is to fold it and install in each pixel. The conventional CCD process technology with double or triple poly-silicon electrodes makes it very difficult to achieve folded CCDs. By utilizing a conventional CMOS process technology with only a single poly-silicon layer consisting of plurality of electrodes with a spacing of 150nm, we can design folded CCDs installed in each pixel. However, it is challenging to realize a practical folded CCD that has sufficient transfer efficiency and reasonable amount of full well capacity. This paper reports a design of folded CCDs for ultra high speed imaging with example simulation results.