Title :
Power-down structures for BIST
Author_Institution :
VLSI Technol. Inc., Tempe, AZ, USA
Abstract :
The author discusses how power-down test structures use a separate test power supply to allow the associated test circuitry to power-down when not being tested. These structures are specially designed to self-isolate from the host circuit when power is removed from Tvdd. This action will increase reliability by removing auxiliary circuit elements used for test from the host design during normal operation and decrease power consumption
Keywords :
VLSI; built-in self test; VLSI testing; built-in self test; host design; power-down test structures; reliability; test circuitry; Built-in self-test; Circuit testing; Controllability; Integrated circuit testing; Logic circuits; Logic design; Logic devices; Logic testing; Observability; Power supplies;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2270-9
DOI :
10.1109/ICCD.1991.139895
