Implementation of AES/Rijndael on a dynamically reconfigurable architecture

Author

Mucci, Claudio ; Vanzolini, Luca ; Lodi, Andrea ; Deledda, Antonio ; Guerrieri, Roberto ; Campi, Fabio ; Toma, Mario

Author_Institution

ARCES, Bologna Univ.

fYear

2007

fDate

16-20 April 2007

Firstpage

1

Lastpage

6

Abstract

Reconfigurable architectures provide the user the capability to couple performance typical of hardware design with the flexibility of the software. This paper presents the design of AES/Rijndael on a dynamically reconfigurable architecture. A performance improvement of three order of magnitude was shown compared to the reference code and up to 24times speed-up figure wrt fast C implementations over a RISC processor. A maximum throughput of 546 Mbit/sec is achieved. Compared to prior art, a better energy efficiency with respect to the other programmable solutions was shown, obtaining up to 3 Mbit/sec/mW

Keywords

cryptography; logic arrays; 546 Mbit/s; AES; Rijndael algorithm; advance encryption standard; dynamically reconfigurable architecture; energy efficient; Computer architecture; Cryptography; Data security; Field programmable gate arrays; Hardware; NIST; Reconfigurable architectures; Reduced instruction set computing; Software performance; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07

Conference_Location

Nice

Print_ISBN

978-3-9810801-2-4

Type

conf

DOI

10.1109/DATE.2007.364617

Filename

4211822