Silicon-based passive inductors

This work presents a CMOS compatible method to develop suspended inductors. In other words, if analytical models for designing planar inductors do not take into account unwanted effects (due to the silicon substrate), our proposal is to etch the substrate in order to match both numerical results and experimental data. The accuracy in the inductance value is required not only to develop a design model, but a component with the lowest mismatch. This characteristic is needed in high frequency applications, where Voltage-Controlled Oscillators (VCOs) and Low Noise Amplifiers (LNAs) are some examples. The inductor, a planar one, is developed according technological design rules of standard CMOS 5-V process. Experimental data of silicon etch based on potassium hydroxide solutions show the viability of this proposal, where a unique silicon nitride mask for transferring a suitable layout pattern was required. By controlling the etch process a 26μm gap, between the nitride layer and the bottom of the silicon substrate, was obtained.