DocumentCode
2641060
Title
Toward a Scalable Test Methodology for 2D-mesh Network-on-Chips
Author
Petersén, Kim ; Öberg, Johnny
Author_Institution
Dept. of Electron. Comput. & Software Syst., R. Inst. of Technol., Kista
fYear
2007
fDate
16-20 April 2007
Firstpage
1
Lastpage
6
Abstract
This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the NoC are tested with BIST, running at full clock-speed, and in a functional-like mode. The BIST is carried out as a go/no-go BIST operation at start up, or on command. It is shown that the proposed methodology can be applied for different implementations of deflecting switches, and that the test time is limited to a few thousand-clock cycles with fault coverage close to 100%
Keywords
built-in self test; integrated circuit interconnections; integrated circuit testing; logic testing; network-on-chip; 2D-mesh network-on-chips; BIST strategy; NoC interconnect network; deflecting switches; scalable test methodology; Built-in self-test; Clocks; Computer networks; Electronic equipment testing; Life testing; Manufacturing; Network-on-a-chip; Software testing; Switches; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Conference_Location
Nice
Print_ISBN
978-3-9810801-2-4
Type
conf
DOI
10.1109/DATE.2007.364619
Filename
4211824
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