Current reference for energy harvesting: 50um per side, At 70 nW, regulating to 125C

Suitable for ultra low power applications, including energy harvesting, the proposed current reference belongs to a resistor-free category of CMOS circuits that combines a PTAT signal dependent on V_T and CTAT signal dependent on MOSFET´s μ to generate a relatively temperature and V_TH independent current source. The proposed topology delivers a 10 nA current reference that consumes under 70 nW of power operating with a V_DD as low as 0.65V. At about 45um by 55um, it is 4 to 50 times smaller in size, compared to prior art current references in its category, and it has a temperature span that exceeds 125C versus about 80C limit for most of its comparable alternatives, according to Monte Carlo simulations. Higher temperature span is achieved by (1) Sensing the PTAT voltage and forcing the I_r at the gate and not the source of the reference current loop, (2) employing differential source followers to generate a larger PTAT voltage instead of prior art use of either asymmetric current mirrors or scaled self-cascode, and (3) using donut shaped equal W/L transistors to minimize drain size for less leakage current. Larger PTAT voltage helps desensitize I_r from offsets (due to V_TH and W/L mismatches associated with transistors in current mirror and loop amplifier). The proposed topology allows for elimination of asymmetric transistors and cascoded current mirrors in the I_r current loop. As a result, compact die size is realized, the impact of source-drain junction leakages is reduced substantially, and hot temperature span is extended. MC simulations, and analysis verifies that TC of about ± 350 ppm/C over a 150C temperature span is achievable, and VC of about ± 0.1% /V in 180nm standard digital CMOS.