Title :
A low-power 20Gb/s transmitter in 65nm CMOS technology
Author :
Nazari, Meisam Honarvar ; Emami-Neyestanak, Azita
Author_Institution :
California Inst. of Technol., Pasadena, CA, USA
Abstract :
A 20Gb/s transmitter employing an analog filtering pre-emphasis equalization technique is presented. The transmitter dissipates 10mW from a 1.2V supply and occupies 0.01mm2. This high-frequency boosting equalization technique allows for compensating channel losses up to 20dB at Nyquist-rate. The prototype was fabricated in 65nm CMOS technology and characterized using lossy cables and 5" and 10" FR4 PCB traces.
Keywords :
CMOS analogue integrated circuits; channel estimation; low-power electronics; printed circuits; radio transmitters; wireless channels; CMOS technology; FR4 PCB traces; analog filtering preemphasis equalization technique; bit rate 20 Gbit/s; channel loss compensation; high-frequency boosting equalization technique; lossy cables; low-power transmitter; size 65 nm; voltage 1.2 V; CMOS integrated circuits; CMOS technology; Finite impulse response filter; Inductors; Loss measurement; Radio transmitters; Transmitter; equalization; intersymbol interference (ISI); pre-emphasis;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-0413-9
Electronic_ISBN :
1529-2517
DOI :
10.1109/RFIC.2012.6242252
