Hardware architecture for real time H.264 CABAC decoding for HDTV applications

H.264 or AVC (Advanced Video Coding) is a latest digital video codec standard which was developed as an answer to the growing demand for better compression in a wide range of applications and for improved network friendliness. H.264 is able to deliver a compression efficiency of up to 50% over a wide range of bit rates and video resolutions compared to previous standards (e.g. MPEG2 or H.263). The downside is that the H.264 decoder complexity is nearly four times higher than the previous standards. Hence a powerful hardware platform is required to provide real-time performance of H.264 in today´s high-end applications like HDTV. We present an innovative Hardware architecture to perform real-time H.264 CABAC decoding using Finite State Machines (FSMs) for decoding of syntax elements. This architecture delivers a throughput of 1 bin per cycle @ 180MHz as reported by Synopsys Design Compiler.