Improving the Fault Tolerance of Nanometric PLA Designs

Several alternative building blocks have been proposed to replace planar transistors, among which a prominent spot belongs to nanometric filaments such as silicon nanowires (SiNWs) and carbon nanotubes (CNTs). However, chips leveraging these nanoscale structures are expected to be affected by a large amount of manufacturing faults, way beyond what chip architects have learned to counter. In this paper, the authors show a design flow, based on software mapping algorithms, to improve the yield of nanometric programmable logic arrays (PLAs). While further improvements to the manufacturing technology will be needed to make these devices fully usable, our flow can significantly shrink the gap between current and desired yield levels. Also, the approach does not need post-fabrication functional analysis and mapping, therefore dramatically cutting on verification costs. The authors check PLA yields by means of an accurate analyzer after Monte Carlo fault injection. The authors show that, compared to a baseline policy of wire replication, they achieve equal or better yields (8% over a set of designs) depending on the underlying defect assumptions