DocumentCode
2641635
Title
Efficient fast algorithm and FPSoC for integer and fractional motion estimation in H.264/AVC
Author
Ndili, Obianuju ; Ogunfunmi, Tokunbo
Author_Institution
Dept. of Electr. Eng., Santa Clara Univ., Santa Clara, CA, USA
fYear
2011
fDate
9-12 Jan. 2011
Firstpage
407
Lastpage
408
Abstract
In this paper we propose an efficient motion estimation algorithm as well as its supporting FPGA-based, field programmable system-on-chip (FPSoC), for integer and fractional motion estimation. Our results show that the rate-distortion loss of our algorithm is insignificant when compared to full search in H.264/AVC, while our FPSoC is hardware-efficient, even out-performing some state-of-the-art ASIC implementations.
Keywords
field programmable gate arrays; motion estimation; rate distortion theory; system-on-chip; video coding; FPGA; FPSoC; H.264/AVC standard; field programmable system-on-chip; fractional motion estimation; integer motion estimation; rate-distortion; Algorithm design and analysis; Automatic voltage control; Computer architecture; Conferences; IP networks; Motion estimation; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics (ICCE), 2011 IEEE International Conference on
Conference_Location
Las Vegas, NV
ISSN
2158-3994
Print_ISBN
978-1-4244-8711-0
Type
conf
DOI
10.1109/ICCE.2011.5722654
Filename
5722654
Link To Document