A wideband fractional-N PLL with suppressed charge-pump noise and automatic loop filter calibration

This paper discusses the design of a wideband fractional-N frequency synthesizer. The adoption of a bang-bang phase detector and a two-path loop filter reduces the impact of charge-pump noise to negligible levels with no penalty on power dissipation and enables a novel scheme for the calibration of the loop filter parameters over process spreads. The 3.0-to-4.0-GHz synthesizer fully integrated in a 65-nm CMOS technology consumes 5 mW from a 1.2-V voltage supply. The flat in-band noise is -104 dBc/Hz over a 5.5-MHz bandwidth and the reference spur level is -71 dBc at 40 MHz. The maximum in-band fractional spur for near-integer channels is -42 dBc. The core area occupation is 0.22 mm².