A noise test structure for CMOS logic families

In high performance CMOS VLSI circuit design, a problem which is no longer negligible is self-induced noise due to simultaneous switching of a large amount of gates. This leads to the necessity to have a tool which is able to evaluate the variation of the reference value of power and ground lines and, as a consequence, the effect that this noise induces in both the digital gates connected to the same lines or in neighbouring lines via crosstalk effects, and in the analog circuits due to substrate noise in mixed-signal design. This paper describes the structure of a test IC for noise tolerance measurements in high speed CMOS logic families. Integrated inductors and ground bounce effects are used to internally generate and inject noise to a device under test. The energy and timing sequence of noise events are controlled by a matrix of programmable control signals. The effect of the noise injected is measured by a detection structure in terms of logic errors and compared with the results of a simulation tool for the evaluation of noise tolerance in CMOS logic families.