Functional verification of multi-million gates ASICs for designing communications networks: trends, tools and techniques

In this paper, we present a survey of tools and techniques used for verification of complex multi-million gate application specific integrated circuits (ASICs). We are particularly interested in the verification of ASICs that are used for designing communications networks such as switch/routers. With tremendous increase in gate count, verification of ASICs has become a major challenge and one of the greatest design concerns. A new VLSI design methodology that takes into account verification issues in the early phase of design and utilizes state-of-the-art techniques has become a necessity.