Novel Test Infrastructure and Methodology Used for Accelerated Bring-Up and In-System Characterization of the Multi-Gigahertz Interfaces on the Cell Processor

Design-for-test (DFT) techniques are continuously used in designs to help identify defects during silicon manufacturing. However, prior to production, a significant amount of time and effort is needed to bring-up and validate various aspects of the silicon design in the system. In particular, the use of multi-Gigabit I/O signaling for a high I/O count, high-volume product introduces unique test challenges during these two phases of the product life cycle. In this paper, we shall discuss the test infrastructure and methodologies used to accelerate bring-up and in-system silicon characterization for high-speed mixed-signal I/O. These ideas will lead to a shortened time to market (TTM) at a lower cost. As a case study, we shall illustrate these techniques used in the development of the Rambus FlexIOtrade processor bus and XIOtrade memory interface used on the first generation Cell processor (aka Cell Broadband Enginetrade or Cell BE). Cell was co-developed by Sony Corporation, Sony Computer Entertainment Inc, Toshiba Corporation, and IBM and is used in the Sony Play Stationreg 3 (PS3trade) game console and other intense computational applications. The Cell processor uses 5Gbps links for the processor´s FlexIO system interface and 3.2Gbps links for the processor´s XDRtrade memory interface. This per pin bandwidth translates into a system interface with a bandwidth of 60GB/s and a memory interface with a bandwidth of 25.6GB/s, respectively