Title :
An IF digitizer IC employing a continuous-time bandpass delta-sigma ADC
Author :
Schreier, R. ; Shibata, H. ; Hendriks, P. ; Aliroteh, M. ; Kozlov, V. ; Tong, H.K. ; Del Muro, A. ; Shrestha, P. ; Caldwell, T. ; Alldred, D. ; Yang, W. ; Paterson, D. ; Lai, P.W.
Author_Institution :
Analog Devices, Inc., Toronto, ON, Canada
Abstract :
A 65-nm CMOS IC containing a synthesizer, a continuous-time bandpass delta-sigma ADC and associated digital filter digitizes 200-400 MHz inputs with bandwidths up to 100 MHz. With the ADC clock supplied by the internal synthesizer, the observed phase noise on a 430-MHz carrier is -137 dBc/Hz at 750-kHz offset. The gain of the IC is adjustable over a 39-dB range using an LNA in parallel with a resistive attenuator. The IC achieves NF = 7.5/26 dB and IIP3 = 8/36 dBm at the ±12-dB gain settings. The ADC´s continuous-time architecture provides inherent alias protection, with ~70 dB of alias attenuation observed in practice. The IC consumes 1 W from 1.0-V and ±2.5-V supplies.
Keywords :
CMOS integrated circuits; UHF filters; UHF integrated circuits; VHF filters; analogue-digital conversion; attenuators; band-pass filters; clocks; continuous time filters; delta-sigma modulation; digital filters; low noise amplifiers; phase noise; CMOS IC synthesizer; IF digitizer IC; LNA; continuous-time bandpass delta-sigma ADC clock; digital filter; frequency 200 MHz to 400 MHz; frequency 430 MHz; gain -12 dB; gain 12 dB; noise figure 26 dB; noise figure 7.5 dB; phase noise; power 1 W; resistive attenuator; size 65 nm; voltage -2.5 V; voltage 1.0 V; voltage 2.5 V; Attenuation; Attenuators; Clocks; Integrated circuits; Noise measurement; Receivers; Synthesizers; IF digitizer; analog-to-digital converter; bandpass ADC; delta-sigma ADC; software radio; superheterodyne receiver;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-0413-9
Electronic_ISBN :
1529-2517
DOI :
10.1109/RFIC.2012.6242291
