DocumentCode
2642273
Title
F-RISC/I: fast reduced instruction set computer with GaAs (H) MESFET implementation
Author
Tien, C.K. ; Poon, C.C. ; Greub, H. ; McDonald, J.F.
Author_Institution
Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
fYear
1991
fDate
14-16 Oct 1991
Firstpage
293
Lastpage
296
Abstract
F-RISC/I is a monolithic GaAs microprocessor with a seven stage pipeline implemented with SBFL standard cells. It is targeted at a clock rate of 400 MHz with a CPI of 1.45. The impacts of GaAs technology on system architecture, CPU architecture, circuit level optimization, implementation, performance, and testing of F-RISC/I are discussed. The GaAs technology environment is investigated and compared to that of Si
Keywords
III-V semiconductors; VLSI; field effect integrated circuits; gallium arsenide; microprocessor chips; reduced instruction set computing; 400 MHz; CPU architecture; F-RISC/I; GaAs; MESFET; SBFL standard cells; circuit level optimization; fast reduced instruction set computer; implementation; microprocessor; performance; system architecture; CMOS technology; Capacitance; Circuits; Computer aided instruction; FETs; Gallium arsenide; Logic; MESFETs; Microprocessors; Pipelines;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-2270-9
Type
conf
DOI
10.1109/ICCD.1991.139901
Filename
139901
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