Title :
A 14.1-GHz dual-modulus prescaler in 130nm CMOS technology using sequential implication logic cells
Author :
Chen, Wu-Hsin ; Roa, Elkim ; Loke, Wing-Fai ; Jung, Byunghoo
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
In this work, we demonstrate the use of a non-traditional logic for the implementation of a dual-modulus prescaler. The proposed prescaler consumes less power than TSPC designs and is faster than ETSPC designs. The maximum speed reaches up to 96% of that of a single divide-by-2 D-flip-flop, the theoretical limit. Implemented in 130-nm CMOS technology, the maximum input frequency reaches 14.1GHz with a power consumption of 1.2mW.
Keywords :
CMOS logic circuits; field effect MMIC; flip-flops; logic design; prescalers; CMOS technology; ETSPC designs; TSPC designs; dual-modulus prescaler; frequency 14.1 GHz; nontraditional logic; power 1.2 mW; power consumption; sequential implication logic cells; single divide-by-2 D-flip-flop; size 130 nm; CMOS integrated circuits; CMOS technology; Clocks; Delay; Logic gates; Power demand; Transistors;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-0413-9
Electronic_ISBN :
1529-2517
DOI :
10.1109/RFIC.2012.6242295
