• DocumentCode
    2642366
  • Title

    Soft-core Processor Customization using the Design of Experiments Paradigm

  • Author

    Sheldon, David ; Vahid, Frank ; Lonardi, Stefano

  • Author_Institution
    Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA
  • fYear
    2007
  • fDate
    16-20 April 2007
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Parameterized components are becoming more commonplace in system design. The process of customizing parameter values for a particular application, called tuning, can be a challenging task for a designer. Here we focus on the problem of tuning a parameterized soft-core microprocessor to achieve the best performance on a particular application, subject to size constraints. We map the tuning problem to a well-established statistical paradigm called design of experiments (DoE), which involves the design of a carefully selected set of experiments and a sophisticated analysis that has the objective to extract the maximum amount of information about the effects of the input parameters on the experiment. We apply the DoE method to analyze the relation between input parameters and the performance of a soft-core microprocessor for a particular application, using only a small number of synthesis/execution runs. The information gained by the analysis in turn drives a soft-core tuning heuristic. We show that using DoE to sort the parameters in order of impact results in application speedups of 6times-17times versus an un-tuned base soft-core. When compared to a previous single-factor tuning method, the DoE-based method achieves 3times-6times application speedups, while requiring about the same tuning runtime. We also show that tuning runtime can be reduced by 40-45% by using predictive tuning methods already built into a DoE tool
  • Keywords
    design of experiments; microprocessor chips; design of experiments; soft core microprocessor; system design; tuning heuristic; Application specific integrated circuits; Circuit optimization; Computer science; Field programmable gate arrays; Hardware; Information analysis; Integrated circuit synthesis; Integrated circuit technology; Microprocessors; Runtime;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
  • Conference_Location
    Nice
  • Print_ISBN
    978-3-9810801-2-4
  • Type

    conf

  • DOI
    10.1109/DATE.2007.364392
  • Filename
    4211902