Vertical and planar merged MOS transistors for low-voltage high-speed ULSI

Author

Bubennikov, Alexander N. ; Rakitin, Vladimir V. ; Zykov, Andrey V.

Author_Institution

Moscow Inst. of Phys. & Technol., Russia

fYear

1999

fDate

22-24 Nov. 1999

Firstpage

251

Lastpage

254

Abstract

Novel vertical and planar merged MOS (VMMOS and PMMOS) structures which increase the packaging density for advanced high-speed low-voltage low-power ULSI are examined. The VMMOS and PMMOS, where electrons and holes move along common channels, are simulated using 2D-numerical device-circuit simulators (DCS). Various VMMOS and PMMOS-SOI constructions providing integration density of up to 10⁹ elements/cm² (0.1 μm design rule) at supply voltages of 0.2-0.8 V have been simulated and optimized.

Keywords

CMOS integrated circuits; MOSFET; ULSI; circuit simulation; high-speed integrated circuits; low-power electronics; numerical analysis; optimisation; semiconductor device models; 0.1 micron; 0.2 to 0.8 V; 2D-numerical device-circuit simulators; CMOS technology; PMMOS structures; PMMOS-SOI constructions; VMMOS structures; VMMOS-SOI constructions; design rule; electron/hole common channels; high-speed low-voltage low-power ULSI; integration density; low-voltage high-speed ULSI; optimization; packaging density; planar merged MOS transistors; simulation; supply voltage; vertical merged MOS transistors; CMOS technology; Charge carrier processes; Circuit simulation; Design optimization; Information systems; Low voltage; MOSFETs; Numerical simulation; Packaging; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 1999. ICM '99. The Eleventh International Conference on

Print_ISBN

0-7803-6643-3

Type

conf

DOI

10.1109/ICM.2000.884851

Filename

884851