Title :
A new faster and simpler systolic structure for IIR filters
Author :
Lapointe, Marcel ; Fortier, Paul ; Huynh, Huu Tuê
Author_Institution :
Dept. de Genie Electrique, Laval Univ., Que., Canada
Abstract :
A bit-level systolic array architecture is presented for implementing infinite impulse response (IIR) filters. The topology is regular and modular, which makes the VLSI design easier. This realization has simpler hardware and a faster iteration period in comparison with a previous realization. In this case, the single coefficient of a one-pole filter covers the entire range of stability without increasing the array delay. Conventional full adders, multiplexers, and latches are the only type of base cell to be used in the array
Keywords :
VLSI; digital filters; systolic arrays; IIR filters; VLSI; adders; array delay; bit-level systolic array architecture; infinite impulse response; iteration period; latches; multiplexers; one-pole filter; stability; systolic structure; topology; Arithmetic; Delay; Hardware; IIR filters; Pipeline processing; Stability; Systolic arrays; Throughput; Topology; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112351
