5.8 GHz low-flicker-noise CMOS direct-conversion receiver using deep-n-well vertical-NPN BJT

Author

Hsiao, Yu-Chih ; Meng, Chinchun ; Syu, Jin-Siang ; Wang, Chia-Ling ; Wong, Shyh-Chyi ; Huang, Guo-Wei

Author_Institution

Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2012

fDate

17-19 June 2012

Firstpage

467

Lastpage

470

Abstract

This paper demonstrates a 5.8 GHz low-power, low-flicker-noise direct-conversion receiver using deep-n-well vertical-NPN BJT based subharmonic Gilbert mixer. The deep-n-well vertical-NPN BJT is placed in the LO switching core of the bottom-level subharmonic mixer and the input transconductance stage of the subsequent IF VGA. As a result, the flicker noise corner is improved and the noise figure is 9.5 dB at IF=100 kHz. The maximum gain reaches 50 dB in the operated frequency. The total power consumption is 10 mW at 1.8 V supply voltage.

Keywords

CMOS integrated circuits; MMIC amplifiers; MMIC mixers; field effect MMIC; flicker noise; microwave bipolar transistors; microwave receivers; IF VGA; LO switching core; bottom-level subharmonic mixer; deep-N-well vertical-NPN BJT; deep-n-well vertical-NPN BJT; frequency 100 kHz; frequency 5.8 GHz; gain 50 dB; input transconductance stage; low-flicker-noise CMOS direct-conversion receiver; noise figure; noise figure 9.5 dB; power 10 mW; subharmonic Gilbert mixer; variable gain amplifier; voltage 1.8 V; 1f noise; CMOS integrated circuits; Gain; Mixers; Radio frequency; Receivers; direct-conversion receiver; low power; subharmonic mixer; vertical-NPN bipolar junction transistor;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE

Conference_Location

Montreal, QC

ISSN

1529-2517

Print_ISBN

978-1-4673-0413-9

Electronic_ISBN

1529-2517

Type

conf

DOI

10.1109/RFIC.2012.6242323

Filename

6242323