Display Verification IP Core Design Based on Star-Extraction and Star-Recognition Image Processing on FPGA

Author

Sheng, Linyang ; Shao, Jingbo ; Xu, Min ; Cui, Yuanquan

Author_Institution

Coll. of Comput. Sci. & Inf. Eng., Harbin Normal Univ., Harbin, China

fYear

2011

fDate

June 30 2011-July 2 2011

Firstpage

151

Lastpage

155

Abstract

This paper presents FPGA based VGA display interface design for image display verification during test procedure in the star sensor debugging phase. Methods of asynchronous FIFO, methods for data update during line blanking interval and vertical blanking interval were adopted, and CCD camera´s requirements for special sequential order were satisfied, and the metastable state problem caused by data´s cross clock domain were solved. Experiment results show that the system provides effective verification platform for ground function test of star sensor.

Keywords

CCD image sensors; astronomical image processing; attitude measurement; computer displays; field programmable gate arrays; image recognition; CCD camera; FPGA; VGA display interface design; asynchronous FIFO; cross clock domain; display verification IP core design; ground function test; image display verification; line blanking interval; metastable state problem; star extraction; star recognition image processing; star sensor debugging phase; test procedure; vertical blanking interval; Blanking; Cameras; Charge coupled devices; Field programmable gate arrays; Pixel; Random access memory; Timing; FPGA; IP core; embedded system; star identification; star sensor;

fLanguage

English

Publisher

ieee

Conference_Titel

Innovative Mobile and Internet Services in Ubiquitous Computing (IMIS), 2011 Fifth International Conference on

Conference_Location

Seoul

Print_ISBN

978-1-61284-733-7

Electronic_ISBN

978-0-7695-4372-7

Type

conf

DOI

10.1109/IMIS.2011.44

Filename

5976153