Design methodologies impact on the embedded system performances: Case of cryptographic algorithm

Due to their flexible architecture, lower-cost and faster processing, Field Programmable Gate Arrays (FPGAs) provide the ability to implement a Programmable System-On-Chip (SoPC) on a single FPGA which include one or more hard-core or soft-core microprocessors. The programmable logic fabric of the FPGA can be used to implement complex embedded applications using three design methodologies. The first is based on software implementation using soft-core microprocessors that give designers the ability to adapt many configured elements to their specific application including memory subsystems, interrupt handling, ISA features, etc. The second is based on hardware implementation using traditional CAD tools. And the third is based on both software/hardware co-design methodology using coprocessors in order to accelerate the design process. This paper proposes a performance evaluation of these design methodologies on a complex secure application such as lightweight cryptographic hash functions. According to their high computationally intensive in FPGA-Based systems and their growing demand in different applications such as networks authentications, SCADA (Supervision Control and Data Acquisition) systems, Digital Signal Standard (DSS), lightweight cryptographic hash functions present the most appropriate choice to evaluate our design methodologies.