Title :
A 0.6–7 Gbps, 1/7 rate, burst mode clock and data recovery circuit and demultiplexer
Author :
Chen, Yu-Hsian ; Chen, Wei-Zen
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
A 1/7 rate, burst mode clock and data recovery circuit incorporating with demultiplexer is proposed. It covers 622 Mbps to 7 Gbps operation by selective-gating digitally controlled oscillator for phase synchronization and digital frequency-locked loop for frequency tracking. The latency for data recovery and 1:7 demultiplexing is less than 10 bit periods. Incorporating both CDR and demultiplexer, this chip consumes 1.5 mW, 6 mW, and 17 mW respectively at 622 Mbps, 2488Mbps, and 7Gbps operations. Implemented in a 90 nm CMOS technology, the chip area is 1.162 × 1.205 mm2.
Keywords :
CMOS analogue integrated circuits; MMIC oscillators; UHF oscillators; clock and data recovery circuits; demultiplexing equipment; field effect MMIC; frequency locked loops; synchronisation; CDR; CMOS technology; bit rate 0.6 Gbit/s to 7 Gbit/s; burst mode clock and data recovery circuit; data recovery; demultiplexer; digital frequency-locked loop; frequency tracking; phase synchronization; power 1.5 mW; power 17 mW; power 6 mW; selective-gating digitally-controlled oscillator; size 90 nm; Clocks; Computer architecture; Frequency control; Frequency locked loops; Logic gates; Oscillators; Timing; digital controlled oscillator; frequency locked loop; phase locked loop;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-0413-9
Electronic_ISBN :
1529-2517
DOI :
10.1109/RFIC.2012.6242339
