DocumentCode :
2643403
Title :
Hardware software partitioning with integrated hardware design space exploration
Author :
Srinivasan, Vinoo ; Radhakrishnan, Shankar ; Vemuri, Ranga
Author_Institution :
Dept. of Electr. Comput. & Eng. Comput. Sci., Cincinnati Univ., OH, USA
fYear :
1998
fDate :
23-26 Feb 1998
Firstpage :
28
Lastpage :
35
Abstract :
This paper presents an integrated approach to hardware software partitioning and hardware design space exploration. We propose a genetic algorithm which performs hardware software partitioning on a task graph while simultaneously contemplating various design alternatives for tasks mapped to hardware. We primarily deal with data dominated designs typically found in digital signal processing and image processing applications. A detailed description of various genetic operators is presented. We provide results to illustrate the effectiveness of our integrated methodology
Keywords :
directed graphs; genetic algorithms; high level synthesis; digital signal processing; genetic algorithm; hardware design space exploration; hardware software partitioning; image processing; task graph; Application software; Computer architecture; Costs; Embedded system; Genetic algorithms; Hardware; Simulated annealing; Software performance; Space exploration; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
Type :
conf
DOI :
10.1109/DATE.1998.655833
Filename :
655833
Link To Document :
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