Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width

Author

Coquand, R. ; Cassé, M. ; Barraud, S. ; Leroux, P. ; Cooper, D. ; Vizioz, C. ; Comboroure, C. ; Perreau, P. ; Maffini-Alvaro, V. ; Tabone, C. ; Tosti, L. ; Allain, F. ; Barnola, S. ; Delaye, V. ; Aussenac, F. ; Reimbold, G. ; Ghibaudo, G. ; Munteanu, D. ;

Author_Institution

STMicroelectron., Crolles, France

fYear

2012

fDate

12-14 June 2012

Firstpage

13

Lastpage

14

Abstract

A detailed study of performance in uniaxially-strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial SSOI substrate is presented. 2D strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. For the first time, an improvement of electron mobility in SSOI NW scaled down to 10nm width has been successfully demonstrated (+55% with respect to SOI NW). This improvement is maintained even by using H₂ annealing used for Ω-Gate. On short gate length, a strain-induced I_on gain as high as 40% at L_G=45nm is achieved for multiple-NWs active pattern.

Keywords

annealing; electron mobility; elemental semiconductors; field effect transistors; nanopatterning; nanowires; silicon; Ω-gate; 2D strain imaging; NW transistor; SSOI NW; Si; annealing; biaxial SSOI substrate; electron mobility; lateral strain relaxation; multiple-NWs active pattern; nanoscale patterning; omega-gate nanowire FET; size 10 nm; size 45 nm; strain-induced gain; strain-induced performance enhancement; tri-gate nanowire FET; uniaxially-strained Si nanowire; FETs; MOS devices; Performance evaluation; Silicon; Stress; Uniaxial strain;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2012 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4673-0846-5

Electronic_ISBN

0743-1562

Type

conf

DOI

10.1109/VLSIT.2012.6242437

Filename

6242437