Strained tunnel FETs with record ION: first demonstration of ETSOI TFETs with SiGe channel and RSD

Author

Villalon, A. ; Le Royer, C. ; Cassé, M. ; Cooper, D. ; Prévitali, B. ; Tabone, C. ; Hartmann, J. -M ; Perreau, P. ; Rivallin, P. ; Damlencourt, J. -F ; Allain, F. ; Andrieu, F. ; Weber, O. ; Faynot, O. ; Poiroux, T.

Author_Institution

CEA, LETI, Grenoble, France

fYear

2012

fDate

12-14 June 2012

Firstpage

49

Lastpage

50

Abstract

We present for the first time Tunnel FETs obtained with a FDSOI CMOS process flow featuring High-K Metal Gate, ultrathin body compressively strained Si_1-xGe_x (x from 0 to 30%) based channels, and Si_0.7Ge_0.3 Raised SD. We analyse the tunnelling improvements due to the different technological injection boosters: ultrathin body & EOT, strain, low band gap source, and low temperature SD anneal. For the first time, TFETs with large ON current (up to 428μA/μm) are demonstrated (with >;x1000 I_ON gain vs. SOI).

Keywords

CMOS integrated circuits; Ge-Si alloys; MOSFET; annealing; energy gap; silicon-on-insulator; tunnel transistors; tunnelling; EOT; ETSOI TFET; FDSOI CMOS process flow; ON current; RSD; Si_0.7Ge_0.3; SiGe channel; high-k metal gate; low band gap source; low temperature SD annealing; strained tunnel FET; technological injection boosters; tunnelling improvements; ultrathin body compressive; Annealing; CMOS integrated circuits; Junctions; Logic gates; Silicon; Silicon germanium; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2012 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4673-0846-5

Electronic_ISBN

0743-1562

Type

conf

DOI

10.1109/VLSIT.2012.6242455

Filename

6242455