A simple new write scheme for low latency operation of phase change memory

The behavior of resistance drift after RESET operation for phase change memory (PCRAM) is investigated. We propose, for the first time, an effective way to accelerate the drift so that the program/read latency may better match that for DRAM for SCM (storage class memory) application. By simply applying an extra annealing pulse after RESET we can quickly anneal out many defects (that are responsible for the drift) and provide a drift-free period that enlarges the read window. A physical model is proposed to understand the defect annealing phenomenon, which predicts the resistance drift behavior well.