Design methodology for a MIPS compatible embedded control processor

Author

Peck, Raymond ; Pate, Jay

Author_Institution

LSI Logic Corp., Milpitas, CA, USA

fYear

1991

fDate

14-16 Oct 1991

Firstpage

324

Lastpage

328

Abstract

The design methodology of a 700000-transistor, 50 MHz MIPS-1 compatible embedded control processor, the LR33000, is described. This single chip processor consists of an R3000-compatible CPU, 8 kB of instruction cache, 1 kB of data cache, a DRAM controller, write buffer, timers, and a programmable system interface which directly connects to DRAM, SRAM and PROM. A mix of synthesis and schematic entry, hand and automatic optimization was used for logic design. The short design time and bug-free first-run silicon have demonstrated the success of this design methodology

Keywords

logic CAD; microprocessor chips; reduced instruction set computing; 1 kB; 50 MHz; 8 kB; DRAM controller; LR33000; MIPS compatible embedded control processor; PROM; R3000-compatible CPU; SRAM; bug-free first-run silicon; data cache; design methodology; instruction cache; logic design; optimization; programmable system interface; single chip processor; timers; write buffer; Automatic control; Control system synthesis; Control systems; Design methodology; Design optimization; Logic design; PROM; Process control; Random access memory; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2270-9

Type

conf

DOI

10.1109/ICCD.1991.139909

Filename

139909