Title :
SRAM design in nano-scale CMOS technologies (Invited)
Author :
Zhang, Kevin ; Karl, Eric ; Wang, Yih
Author_Institution :
Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA
Abstract :
SRAM scaling has become increasingly challenging in meeting both power and density requirements. Critical circuit technologies along with key process advancement are discussed in enabling SRAM scaling to continue to follow Moore´s law well into the future.
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit design; Moore law; SRAM design; SRAM scaling; nanoscale CMOS technologies; static random access memory; Arrays; CMOS integrated circuits; CMOS technology; Circuit stability; Logic gates; Random access memory; Transistors;
Conference_Titel :
VLSI Technology (VLSIT), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0846-5
Electronic_ISBN :
0743-1562
DOI :
10.1109/VLSIT.2012.6242473
