Verification techniques for a MIPS compatible embedded control processor

The methods used in the verification of a MIPS-1 architecture-compatible embedded control processor are described. This single-chip processor contains 700000 transistors, operates at 50 MHz, and consists of a CPU core, 8 kB of instruction cache, 1 kB of data cache, a DRAM controller, a write buffer, three timers, and a bus interface unit (BIU). Individual module testing and integrated system testing were the two methods used for verification. Integrated system simulation included architectural, functional, and random instruction testing using behavioral simulation test environments. These techniques provided a comprehensive and effective testing environment. The transfer of fully functional rev A silicon to production demonstrated the success of this methodology