Title :
Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation
Author :
Yamamoto, Y. ; Makiyama, H. ; Tsunomura, T. ; Iwamatsu, T. ; Oda, H. ; Sugii, N. ; Yamaguchi, Y. ; Mizutani, T. ; Hiramoto, T.
Author_Institution :
Low-power Electron. Assoc. & Project (LEAP), Hitachinaka, Japan
Abstract :
We demonstrated Silicon on Thin Buried oxide (SOTB) CMOS especially designed for ultralow-voltage (ULV) operation down to 0.4 V for the first time. Utilizing i) dual-poly gate stack with high-k having quarter-gap work functions best for the ULV CMOS operation, and ii) a novel “local ground plane (LGP)” structure that significantly improves short-channel effect (Vth roll off) without increasing local variability unlike halo for bulk, low-leakage SRAM operation was demonstrated with adaptive-body-bias (ABB) scheme.
Keywords :
CMOS integrated circuits; SRAM chips; low-power electronics; silicon-on-insulator; work function; ABB scheme; LGP structure; SOTB CMOS operation; Si; ULV CMOS operation; adaptive-body-bias scheme; dual-poly gate stack; local ground plane structure; local variability; low-leakage SRAM operation; poly-high-k-SiON gate stack; profile engineering; quarter-gap work functions; short-channel effect; silicon-on-thin buried oxide CMOS; ultralow-voltage operation; ultralow-voltage silicon-on-thin-box CMOS operation; voltage 0.4 V; Hafnium; High K dielectric materials; Logic gates; Random access memory; Silicon; Transistors; Very large scale integration;
Conference_Titel :
VLSI Technology (VLSIT), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0846-5
Electronic_ISBN :
0743-1562
DOI :
10.1109/VLSIT.2012.6242485
