An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization

Reliability characterization is the industrial process intended to measure the useful life period and failure rate of a component population by exploiting stress mechanisms. The paper describes a methodology for the automatic generation of stress programs to be used during the reliability characterization process of Systems-on-Chip (SoC). The proposed methodology is composed of a two-phase strategy, first an evolutionary algorithm (EA) works on the SoC´s description at Register-Transfer-Level (RTL) by evaluating high-level metrics to quickly progress to a sufficient stress quality level, then evolution is continued on the gate-level description towards a better stress quality. The proposed methodology was experimented on a SoC manufactured in a 90nm technology including an 8051 processor. The proposed strategy reduces significantly the generation times and quickly improves the stress quality values with respect to the previous methodology.