Title :
High performance bulk planar 20nm CMOS technology for low power mobile applications
Author :
Shang, Huiling ; Jain, S. ; Josse, E. ; Alptekin, E. ; Nam, M.H. ; Kim, S.W. ; Cho, K.H. ; Kim, I. ; Liu, Y. ; Yang, X. ; Wu, X. ; Ciavatti, J. ; Kim, N.S. ; Vega, R. ; Kang, L. ; Meer, H.V. ; Samavedam, S. ; Celik, M. ; Soss, S. ; Utomo, H. ; Ramachandra
Author_Institution :
Microelectron. Div., Semicond. R&D Center (SRDC), IBM, Hopewell Junction, NY, USA
Abstract :
In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.
Keywords :
CMOS integrated circuits; high-k dielectric thin films; HKMG process; LPM; SNM; ULK dielectrics; advanced high-k metal gate process; competitive R-C; density scaling; frequency improvement; high performance bulk planar CMOS technology; high-density SRAM; low power mobile computing applications; lower standby power; metal pitch; size 20 nm; size 28 nm; static noise margin; strain engineering; voltage 0.9 V; voltage 160 mV; CMOS integrated circuits; Computer architecture; Logic gates; Metals; Microprocessors; Performance evaluation; Random access memory;
Conference_Titel :
VLSI Technology (VLSIT), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0846-5
Electronic_ISBN :
0743-1562
DOI :
10.1109/VLSIT.2012.6242495
