On the technology roadmap of Free-Viewpoint 3DTV receivers

Author

Bondarev, E. ; Miquel, R. ; Imbert, M. ; Zinger, S. ; De With, P.H.N.

Author_Institution

Eindhoven Univ. of Technol., Eindhoven, Netherlands

fYear

2011

fDate

9-12 Jan. 2011

Firstpage

687

Lastpage

688

Abstract

This paper presents the architecture of an innovative 3DTV receiver system, enabling Free-ViewPoint (FVP) interpolation and rendering functionality. We outline the hardware architecture of the receiver, and specify how the design decisions address the extremely high processing requirements of the system. Based on the experience and quantitative data obtained during the receiver prototyping, we present an architecture roadmap for devices with embedded FVP functionality. We identify three major hardware choices for FVP mapping, namely a dedicated hardware unit, FPGA- and GPU solutions, and discuss pros and cons of each choice.

Keywords

computer graphic equipment; coprocessors; field programmable gate arrays; high definition television; television receivers; three-dimensional television; FPGA; FVP mapping; GPU; dedicated hardware unit; embedded FVP functionality; free-viewpoint 3DTV Receivers; free-viewpoint interpolation; high-definition 3D television; innovative 3DTV receiver system; receiver prototyping; rendering functionality; Decoding; Field programmable gate arrays; High definition video; Interpolation; Receivers; Rendering (computer graphics); Streaming media;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics (ICCE), 2011 IEEE International Conference on

Conference_Location

Las Vegas, NV

ISSN

2158-3994

Print_ISBN

978-1-4244-8711-0

Type

conf

DOI

10.1109/ICCE.2011.5722810

Filename

5722810