DocumentCode :
2644585
Title :
Use of Statistical Timing Analysis on Real Designs
Author :
Nardi, A. ; Tuncer, E. ; Naidu, S. ; Antonau, A. ; Gradinaru, S. ; Lin, T. ; Song, J.
Author_Institution :
Magma Design Autom., Santa Clara, CA
fYear :
2007
fDate :
16-20 April 2007
Firstpage :
1
Lastpage :
6
Abstract :
A vast literature has been published on statistical static timing analysis (SSTA), its motivations, its different implementations and their runtime/accuracy trade-offs. However, very limited literature exists on the applicability and the usage models of this new technology on real designs. This work focuses on the use of SSTA in real designs and its practical benefits and limitations over the traditional design flow. The authors introduce two new metrics to drive the optimization: skew criticality and aggregate sensitivity. Practical benefits of SSTA are demonstrated for clock tree analysis, and correct modeling of on-chip-variations. The use of SSTA to cover the traditional corner analysis and to drive optimization is also discussed. Results are reported on three designs implemented on a 90nm technology
Keywords :
integrated circuit design; sensitivity analysis; statistical analysis; timing; 90 nm; aggregate sensitivity; clock tree analysis; skew criticality; statistical static timing analysis; Aggregates; Clocks; Engines; Foundries; Information analysis; Integrated circuit interconnections; Libraries; Robustness; Runtime; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Conference_Location :
Nice
Print_ISBN :
978-3-9810801-2-4
Type :
conf
DOI :
10.1109/DATE.2007.364531
Filename :
4212041
Link To Document :
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