• DocumentCode
    2644657
  • Title

    Designing in scaled technologies: 32 nm and beyond

  • Author

    Kosonocky, Stephen ; Burd, Tom ; Kasprak, Keith ; Schultz, Rich ; Stephany, Ray

  • Author_Institution
    Adv. Micro Devices, Inc., Fort Collins, CO, USA
  • fYear
    2012
  • fDate
    12-14 June 2012
  • Firstpage
    147
  • Lastpage
    148
  • Abstract
    VLSI technology scaling in the 32-nm node and beyond has presented designers with increasing challenges to obtain performance gains, power and area reductions each successive generation. Maximum voltage limits, decreasing interconnect performance, and device changes have forced designers to rethink system and circuit design for enhanced system performance and improved user experience.
  • Keywords
    VLSI; integrated circuit design; nanotechnology; VLSI technology scaling; circuit design; maximum voltage limits; size 32 nm; successive generation; CMOS integrated circuits; Logic gates; Metals; Performance evaluation; Random access memory; Reliability; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology (VLSIT), 2012 Symposium on
  • Conference_Location
    Honolulu, HI
  • ISSN
    0743-1562
  • Print_ISBN
    978-1-4673-0846-5
  • Electronic_ISBN
    0743-1562
  • Type

    conf

  • DOI
    10.1109/VLSIT.2012.6242504
  • Filename
    6242504
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2644657