Improved VC merging in the ATM edge LSRs

Multiprotocol label switching enjoys high level of flexibility so that it can be implemented over any kinds of second and third layer protocols. However, due to the presence of high capacity ATM switches with a rich background, using ATM as switching protocol along with IP as routing protocol in implementation of MPLS switches seems to be the best solution. Nevertheless, ATM imposes some limitation when it is used in an MPLS switch. The most important problem is shortage of VCI/VPI spaces in header of the ATM cells, which label of the cell is encapsulated in them, and VC merging is a technique that helps to overcome this problem. VC merge capable MPLS switches suffer from imposed additional buffer space, additional delay and bursty output, which degrade the performance of the network. The imposed delay becomes even more critical when VC merging is implemented in an input-queued ATM edge LSR. The reason for such situation is the need for using an additional stage of reassembly in the switch structure to prevent cell-interleaving problem. In this paper after introducing what has happened in an ATM edge LSR in terms of VC merging, we propose a novel structure that improves the performance of VC merging by eliminating the second stage of reassembly buffers.