DocumentCode :
2644852
Title :
Ultrafast parallel reconfiguration of 3D-stacked reconfigurable spin logic chip with on-chip SPRAM (SPin-transfer torque RAM)
Author :
Tanaka, T. ; Kino, H. ; Nakazawa, R. ; Kiyoyama, K. ; Ohno, H. ; Koyanagi, M.
Author_Institution :
Dept. of Bioeng. & Robot., Tohoku Univ., Sendai, Japan
fYear :
2012
fDate :
12-14 June 2012
Firstpage :
169
Lastpage :
170
Abstract :
We have developed novel 3D-stacked reconfigurable spin logic chip having ultrafast on-chip SPRAM to overcome drawbacks of conventional reconfigurable LSIs. Two reconfigurable spin logic chips were carefully designed and successfully stacked using 3D integration technology. From the SPRAM cell evaluation, the fastest write speed of 5 ns was obtained in the circuits. To realize higher performance reconfigurable LSIs, parallel reconfiguration was fully demonstrated for the stacked reconfigurable spin logic chips for the first time. Both ultrafast on-chip SPRAM and 3D-stacked structure will open a new era of reconfigurable LSIs.
Keywords :
SRAM chips; logic circuits; 3D integration technology; 3D-stacked reconfigurable spin logic chip; SPRAM cell evaluation; on-chip SPRAM; reconfigurable LSI; spin-transfer torque RAM; ultrafast parallel reconfiguration; Bonding; Gold; Magnetic tunneling; Random access memory; Switches; System-on-a-chip; Torque;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology (VLSIT), 2012 Symposium on
Conference_Location :
Honolulu, HI
ISSN :
0743-1562
Print_ISBN :
978-1-4673-0846-5
Electronic_ISBN :
0743-1562
Type :
conf
DOI :
10.1109/VLSIT.2012.6242515
Filename :
6242515
Link To Document :
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