Demonstration of inter-chip data transmission in a three-dimensional stacked chip fabricated by chip-level TSV integration

Author

Hozawa, Kazuyuki ; Furuta, Futoshi ; Hanaoka, Yuko ; Aoki, Mayu ; Osada, Kenichi ; Takeda, Kenichi ; Lee, Kang Wook ; Fukushima, Takafumi ; Koyanagi, Mitsumasa

Author_Institution

Assoc. of Super-Adv. Electron. Technol. (ASET), Kokubunji, Japan

fYear

2012

fDate

12-14 June 2012

Firstpage

175

Lastpage

176

Abstract

Successful 3D integration of a stacked chip fabricated by a “chip-level through-silicon-via (TSV)” process was confirmed by inter-chip data transmission. According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important for chip-level/via-last TSV integration. That is, the design influences TSV contact resistance, TSV coupling capacitance, and wiring capacitance of the surrounding Cu/low-k interconnections.

Keywords

data communication; integrated circuit interconnections; integrated circuit manufacture; three-dimensional integrated circuits; TSV; chip-level through-silicon-via; electrical properties; inter-chip data transmission; low-k interconnections; three-dimensional stacked chip fabrication; Capacitance; Contacts; Data communication; Metals; Semiconductor device measurement; Through-silicon vias; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2012 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4673-0846-5

Electronic_ISBN

0743-1562

Type

conf

DOI

10.1109/VLSIT.2012.6242518

Filename

6242518