Sub-60 nm deeply-scaled channel length extremely-thin body InxGa1−xAs-on-insulator MOSFETs on Si with Ni-InGaAs metal S/D and MOS interface buffer engineering

We report the first demonstration of sub-60 nm deeply-scaled InGaAs- and InAs-on-insulator MOSFETs on Si substrates with MOS interface buffer engineering and Ni-InGaAs metal source/drain (S/D). The devices provide 400 % I_on enhancement, when comparing to that of an In_0.53Ga_0.47As control device with the same drain-induced-barrier-lowering (DIBL) of 100 mV/V, which is attributable to the mobility enhancement and the S/D parasitic resistance (R_SD) reduction. In addition, InAs-OI MOSFETs with the MOS interface buffer show excellent electrostatic characteristics. A MOSFET with channel length (L_ch) of 55 nm shows small DIBL of 84 mV/V and subthreshold slope (S.S.) of 105 mV/dec, both of which do not significantly degrade with a decrease of L_ch, because of the extremely-thin channel thickness.